Prevalent silicon (Si) wafers or gallium arsenide (GaAs) wafers come on the market mainly as circular wafers for the convenience of handling. Gallium nitride wafers or other nitride wafers will be also produced mainly as circular wafers. Top surfaces of semiconductor wafers shall be polished to obtain mirror wafers. In accordance with purposes, sometimes both top and bottom surfaces will be mirror-polished or sometimes only top surfaces will be mirror-polished.
In addition to the surface grinding and polishing, edges of wafers will be ground or polished. As-cut wafers have harp edges which would cause crack, break and fracture of wafers. Fine fractions would damage or contaminate top surfaces. For preventing wafers from cracking or breaking, edges of wafers are ground or ground/polished. In addition to edges, circumferences (circular outer sides) are sometimes ground/polished. The processing of grinding of edges (including peripheries and circumferences) is called “chamfering” or “bevelling”. “Chamfering” and “bevelling” are synonyms.
Silicon wafers are also chamfered. Nitride wafers, e.g., Si wafers, GaN wafers are different from prevalent silicon wafers in rigidity, fragility, solidity and chemical properties. GaN and other nitride crystals are more rigid, more fragile than Si. It is impossible to chemically etch III group planes of nitride, e.g., Ga-plane of GaN crystals.
Si-chamfering technology cannot directly be applied to GaN-chamfering or other nitride chamfering. Chamfering technology being mature for silicon wafers is useless for GaN wafers and other nitride wafers.
Different kinds of semiconductor wafers require different chamfering techniques. Different optimum chamfering methods suitable for different kinds of semiconductor wafers should be sought out by trial and error.
Patent document (1) Japanese Patent Laying Open No. 2002-356398, “Gallium nitride wafer”, alleged to make first freestanding GaN substrates, which had not existed, by an ELO (Epitaxial Lateral Overgrowth) method, chamfer the GaN substrates and form orientation flats (OF) to the GaN wafers. The ELO method of Patent document (1) employed (111) GaAs wafer undersubstrates. The ELO deposited an SiO2 mask with honeycomb distributing microwindows on the GaAs wafer, grew a GaN thin film in horizontal directions on the mask by an HVPE (Hydride Vapor Phase Epitaxy), decreased dislocations, jointed GaN films on the mask and grew GaN along the c-axis.
The HVPE produced more than 100 μm thick GaN crystals, eliminated the GaAs undersubstrate and obtained a freestanding GaN substrate. An obtained GaN substrate had nearly a square-shape. A circular wafer was obtained by grinding the square-shaped as-grown GaN wafer into a circle. For discriminating orientations and obverse/reverse surfaces, the wafer was provided with an OF (orientation flat) and an IF (identification flat) to a (1-100) plane side or a (2-1-10) plane side.
Patent document (1) Japanese Patent Laying Open No. 2002-356398, “Gallium nitride wafer”, disclosed methods of chamfering a GaN wafer into a slant edge at an oblique angle of 5 degrees to 30 degrees or into a round edge of a radius of 0.1 mm to 0.5 mm. The former case rotates a circular, conical shaped whetstone, brings the whetstone into outer contact with an edge of a GaN wafer, and grinds the sharp edge into a slant of an angle of 5 degrees to 30 degrees. The conical whetstone is a resin-bonding whetstone fixing stationary whetgranules by a resin to the surface of the base.
The latter case rotates a spool-shaped whetstone with an inner half circular section of a radius of 0.1 mm to 0.5 mm, brings an edge of a GaN wafer into outer contact with the whetstone and grinds the edge into a circular section.
It turned out, however, that chamfering by the resin-bonding whetstone was liable to induce break or crack in GaN wafers. “Resin-bonding” means that a resin bonds stationary whetgranules to the surface of a base.
(2) Japanese Patent Laying Open No. 2005-136167 (Filing No. 2003-370430), “Method of producing a nitride semiconductor wafer and Nitride semiconductor wafer”, pointed out a problem that GaN wafers which were produced by growing a thick GaN crystal on a foreign material undersubstrate, removing the undersubstrate and obtaining a freestanding GaN crystal were suffering from large bow caused by big differences of thermal expansion and lattice constant between the undersubstrate material and GaN. The document (2) explained that the bow height difference between the center and circumference reached to ±40 μm to ±100 μm.
Polishing a wafer makes a process-induced degradation layer on the surface of the wafer. The Patent document (2) told that the process-induced degradation layer introduced by polishing has a function of expanding the polished surface. The Patent Document (2) said that the bow of nitride wafers could be reduced by the function. The document (2) said that thinning the process-induced degradation layer by etching decreases the expansion force. Further the document (2) declared that combining both polishing and etching on top and bottom surfaces would decrease the bow of nitride wafers.
When a bottom surface (nitride plane; N-plane) is concavely deformed, bottom surface polishing expands the bottom surface by inducing a process-induced degradation layer on the bottom. The bottom surface is distorted convexly. The direction of bow is reversed. The reverse bow should be suppressed. Thus the process-induced degradation layer is thinned by etching. Bottom expansion stress is reduced with thinning of the bottom process-induced degradation layer. The bow decreases.
The document (2) said that the top surface (Ga-plane) was rigid and difficult to polish. Etching of the top surface was also difficult. The document (2) taught that dry etching by chloride plasma was applicable to the top surface (Ga-plane). Grinding and polishing of a GaN wafer caused a 10 μm thick process-induced degradation layer on a top surface and a 50 μm thick process-induced degradation layer on a bottom surface. The document (2) asserted that the bow could be alleviated by adjusting the thickness of the bottom process-induced degradation layer within a pertinent range by polishing and etching.
Embodiment 1 of the document (2) made a 5 μm top-concave GaN wafer enjoying less bow by producing a 50 μm top-concave GaN as-cut wafer, grinding the top surface for reversing the bow to 30 μm top-convex, dry-etching the top for decreasing the bow to 20 μm top-concave, grinding the bottom and etching the bottom. The document (2) declared that a pertinent series of grinding and etching could finally reduce the bow of GaN wafers within a range of +30 μm to −20 μm in a scale of reducing to 2 inch (50 mm) of diameter.
Plus sign denoted top-convex bow Minus sign denoted top-concave bow. The document (2) asserted that the bow of GaN wafers could be suppressed within the scope from 30 μm top-convex to 20 μm top-concave.
(3) Japanese Patent Laying Open No. 2004-319951 (Filing No. 2003-275935), “Edge-polished nitride semiconductor wafer, edge-polished GaN free standing substrate wafer and method of processing an edge-polished nitride semiconductor wafer”, pointed out that chamfering of a GaN wafer by a resin-bonding diamond whetstone being in outer contact with an edge of the GaN wafer induced cracks or breaks of wafers, since GaN is fragile and hard. The document (3) denied resin-bond whetstone chamfering.
The document (3) proposed a whettape chamfering method by preparing a whettape with a tape having stationary whetgranules, bringing an edge in a circular direction in inner-contact with the whettape, rotating the wafer and bevelling the edge by the whettape. The whettape rolls off one spool onto another, in order to expose a new part of the whettape surface. When the stationary granules were worn out, the contacting part is renewed by feeding the edge with a fresh part of the whettape for maintaining the same condition of whetting. Since the edge was in inner contact with the whettape, the contact pressure was small and no shock acted on the edge. The document (3) alleged that the whettape could enhance the yield far higher than the outer-contacting resin-bonding whetstone.
FIG. 11 is a perspective view of the whettape chamfering first proposed by the document (3) (Japanese Patent Laying Open No. 2004-319951). FIG. 12 is an enlarged sectional view of a contacting whettape and an edge of a wafer.
A wafer W is fixed to a rotary disc (not shown in the figure) by vacuum chucking. An edge E of the wafer W is in inner contact with the whettape T. A central angle of the contacting part is 40 degrees to 90 degrees. The document (3) asserted that soft contact of the edge with the elastic whettape could prevent the edge from cracking and breaking.
Document (1)=Japanese Patent Laying Open No. 2002-356398, “Gallium Nitride wafer” (Filing No. 2001-166904).
Document (2)=Japanese Patent Laying Open No. 2005-136167, “Method of producing Nitride semiconductor wafers and Nitride semiconductor wafer. (Filing No. 2003-370430).
Document (3)=Japanese Patent Laying Open No. 2004-319951, “Edge polished Nitride semiconductor wafer and method of processing an edge polished GaN freestanding wafer and a method of chamfering a nitride semiconductor wafer” (Filing No. 2003-275935).
Recent development has enabled the vapor phase growth method and liquid phase growth method to produce nitride semiconductor freestanding crystals. It is, however, still difficult for the liquid phase method to make a large nitride crystal. Large freestanding nitride semiconductor as-cut wafers can be produced by growing a thick GaN crystal on a wide undersubstrate, cutting the GaN crystal by a wiresaw and separating the GaN crystal from the undersubstrate. A series of bottom grinding, chamfering and top grinding/polishing convert the as-cut nitride wafers into nitride semiconductor mirror wafers.
Grinding induces a thick (10 μm-50 μm) process-induced degradation layer on the part in contact with a whetstone. Bottom (surface) grinding causes a process-induced degradation layer on the bottom surface. Chamfering (edge grinding) produces a process-induced degradation layer on the edge. Top (surface) grinding induces another process-induced degradation layer on the top surface. The process-induced degradation layer is a surface layer having disorder of the lattice structure. Plenty of dislocations are included in the process-induced degradation layer. The process-induced degradation layer does not mean the inclusion of impurities. It is undesirable for mirror wafers to remain the process-induced degradation layer on the top or bottom surfaces. The top and bottom process-induced degradation layers should be removed by etching. Instead of the top/bottom surfaces, the present invention observes circumference edge grinding (chamfering, bevelling) closely. Chamfering of the prevalent semiconductor wafers, e.g., silicon wafers and GaAs wafers employs resin-bonding or metal-bonding whetstones which bond diamond granules with a resin or a metal to the base. The prevailing resin-bonding whetstones and the metal-bonding whetstones are acute, hard and sturdy. Chamfering time is short. However, diversion of the prevalent resin- or metal-bonding whetstones to GaN chamfering invites breaks and cracks on the GaN wafers at high rates, generates thick process-induced degradation layers and induces large bow. GaN is easily damaged by shock because of high rigidity, low toughness and high fragility. The high crack occurrence rate originates from the fact that the resin- or metal-bonding whetstones have granules rigidly fixed to the bases and the bonding materials cannot absorb the shocks acting on fragile wafer edges by the granules. Frequent cracks and breaks occur on GaN wafers by chamfering with metal- or resin-bonding whetstones. Even in the case of free from break or crack, 20 μm-50 μm thick process-induced degradation layers M and large bow are induced by the metal- or resin-bonding whetstone chamfering. Sometimes the bow curvature radius is less than 1 m. The prevalent resin- or metal-bonding whetstones are inapplicable to chamfering of the highly rigid and highly fragile GaN wafers.
A first purpose of the present invention is to provide a method of chamfering a nitride wafer without breaking and cracking. A second purpose of the present invention is to provide a method of chamfering a nitride wafer without inducing bow. A third purpose of the present invention is to provide a method of chamfering a nitride wafer with a controlled thickness of an edge process-induced degradation layer. A fourth purpose is to provide a method of chamfering a nitride wafer with a high wafer processing yield. A fifth purpose is to provide a method of chamfering a nitride wafer with a high device production yields. A sixth purpose is to provide a nitride wafer with a high device production yield. Outer portions of top and bottom surfaces are called “peripheries” in the present description. The circular side which is perpendicular to the top/bottom is called a “circumference”. A crossing circle between the top/bottom and the circumference is called a “ridge”. A set of a periphery, a ridge and a circumference is called an “edge”.